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The Linux kernel configuration item CONFIG_ARM64_ERRATUM_3194386
has multiple definitions:
arch/arm64/Kconfig
The configuration item CONFIG_ARM64_ERRATUM_3194386:
(none)
This option adds the workaround for the following errata:
* ARM Cortex-A76 erratum 3324349 * ARM Cortex-A77 erratum 3324348 * ARM Cortex-A78 erratum 3324344 * ARM Cortex-A78C erratum 3324346 * ARM Cortex-A78C erratum 3324347 * ARM Cortex-A710 erratam 3324338 * ARM Cortex-A720 erratum 3456091 * ARM Cortex-A725 erratum 3456106 * ARM Cortex-X1 erratum 3324344 * ARM Cortex-X1C erratum 3324346 * ARM Cortex-X2 erratum 3324338 * ARM Cortex-X3 erratum 3324335 * ARM Cortex-X4 erratum 3194386 * ARM Cortex-X925 erratum 3324334 * ARM Neoverse-N1 erratum 3324349 * ARM Neoverse N2 erratum 3324339 * ARM Neoverse-V1 erratum 3324341 * ARM Neoverse V2 erratum 3324336 * ARM Neoverse-V3 erratum 3312417
On affected cores "MSR SSBS, #0" instructions may not affect subsequent speculative instructions, which may permit unexepected speculative store bypassing.
Work around this problem by placing a Speculation Barrier (SB) or Instruction Synchronization Barrier (ISB) after kernel changes to SSBS. The presence of the SSBS special-purpose register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace will use the PR_SPEC_STORE_BYPASS prctl to change SSBS.
If unsure, say Y.
arch/arm64/Kconfig
The configuration item CONFIG_ARM64_ERRATUM_3194386:
(none)
This option adds the workaround for the following errata:
* ARM Cortex-A710 erratam 3324338 * ARM Cortex-A720 erratum 3456091 * ARM Cortex-X2 erratum 3324338 * ARM Cortex-X3 erratum 3324335 * ARM Cortex-X4 erratum 3194386 * ARM Cortex-X925 erratum 3324334 * ARM Neoverse N2 erratum 3324339 * ARM Neoverse V2 erratum 3324336 * ARM Neoverse-V3 erratum 3312417
On affected cores "MSR SSBS, #0" instructions may not affect subsequent speculative instructions, which may permit unexepected speculative store bypassing.
Work around this problem by placing a speculation barrier after kernel changes to SSBS. The presence of the SSBS special-purpose register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace will use the PR_SPEC_STORE_BYPASS prctl to change SSBS.
If unsure, say Y.
arch/arm64/Kconfig
The configuration item CONFIG_ARM64_ERRATUM_3194386:
(none)
This option adds the workaround for ARM Cortex-X4 erratum 3194386.
On affected cores "MSR SSBS, #0" instructions may not affect subsequent speculative instructions, which may permit unexepected speculative store bypassing.
Work around this problem by placing a speculation barrier after kernel changes to SSBS. The presence of the SSBS special-purpose register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace will use the PR_SPEC_STORE_BYPASS prctl to change SSBS.
If unsure, say Y.
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(none)
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