CONFIG_ARM64_ERRATUM_834220: Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)

General informations

The Linux kernel configuration item CONFIG_ARM64_ERRATUM_834220 has multiple definitions:

Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare) found in arch/arm64/Kconfig

The configuration item CONFIG_ARM64_ERRATUM_834220:

• prompt: Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)
• type: bool
• depends on: CONFIG_KVM
• defined in arch/arm64/Kconfig
• found in Linux kernels: 6.9–6.12

Help text

This option adds an alternative code sequence to work around ARM erratum 834220 on Cortex-A57 parts up to r1p2.

Affected Cortex-A57 parts might report a Stage 2 translation fault as the result of a Stage 1 fault for load crossing a page boundary when there is a permission or device memory alignment fault at Stage 1 and a translation fault at Stage 2.

The workaround is to verify that the Stage 1 translation doesn't generate a fault before handling the Stage 2 fault. Please note that this does not necessarily enable the workaround, as it depends on the alternative framework, which will only patch the kernel if an affected CPU is detected.

If unsure, say N.

Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault found in arch/arm64/Kconfig

The configuration item CONFIG_ARM64_ERRATUM_834220:

• prompt: Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault
• type: bool
• depends on: CONFIG_KVM
• defined in arch/arm64/Kconfig
• found in Linux kernels: 4.4–4.20, 5.0–5.19, 6.0–6.8

Help text

This option adds an alternative code sequence to work around ARM erratum 834220 on Cortex-A57 parts up to r1p2.

Affected Cortex-A57 parts might report a Stage 2 translation fault as the result of a Stage 1 fault for load crossing a page boundary when there is a permission or device memory alignment fault at Stage 1 and a translation fault at Stage 2.

The workaround is to verify that the Stage 1 translation doesn't generate a fault before handling the Stage 2 fault. Please note that this does not necessarily enable the workaround, as it depends on the alternative framework, which will only patch the kernel if an affected CPU is detected.

If unsure, say Y.

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The data is retrived from:

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