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The Linux kernel configuration item CONFIG_CXL_BUS
:
CONFIG_PCI
cxl_bus
, cxl_core
CXL is a bus that is electrically compatible with PCI Express, but layers three protocols on that signalling (CXL.io, CXL.cache, and CXL.mem). The CXL.cache protocol allows devices to hold cachelines locally, the CXL.mem protocol allows devices to be fully coherent memory targets, the CXL.io protocol is equivalent to PCI Express. Say 'y' to enable support for the configuration and management of devices supporting these protocols.
Numeric ID (from LKDDb) and names (from pci.ids) of recognized devices:
05
("Memory controller"), subclass: 02
("CXL"), prog-if: 10
("CXL Memory Device (CXL 2.x)")05
("Memory controller"), subclass: 02
("CXL"), prog-if: 10
("CXL Memory Device (CXL 2.x)")05
("Memory controller"), subclass: 02
("CXL"), prog-if: 10
("CXL Memory Device (CXL 2.x)")Raw data from LKDDb:
lkddb acpi "ACPI0017" : CONFIG_CXL_ACPI CONFIG_CXL_BUS : drivers/cxl/acpi.c # in 5.14–5.18, 5.18+HEAD
lkddb module cxl_bus CONFIG_CXL_BUS : drivers/cxl/Kconfig : "CXL (Compute Express Link) Devices Support" # in 5.12–5.13
lkddb module cxl_core CONFIG_CXL_BUS : drivers/cxl/Kconfig : "CXL (Compute Express Link) Devices Support" # in 5.14–5.19, 6.0–6.12
lkddb pci .... .... .... .... 050210 : CONFIG_CXL_BUS CONFIG_CXL_MEM : drivers/cxl/mem.c # in 5.12–5.13
lkddb pci .... .... .... .... 050210 : CONFIG_CXL_BUS CONFIG_CXL_MEM : drivers/cxl/pci.c # in 5.14–5.17, 5.17+HEAD
lkddb pci .... .... .... .... 050210 : CONFIG_CXL_BUS CONFIG_CXL_PCI : drivers/cxl/pci.c # in 5.18, 5.18+HEAD
lkddb platform "" : CONFIG_CXL_ACPI CONFIG_CXL_BUS : drivers/cxl/acpi.c # in 5.14–5.18, 5.18+HEAD
This page is automaticly generated with free (libre, open) software lkddb(see lkddb-sources).
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Automatically generated (in year 2024). See also LKDDb sources on GitLab