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CONFIG_TIDSPBRIDGE_CACHE_LINE_CHECK: Check buffers to be 128 byte aligned

General informations

The Linux kernel configuration item CONFIG_TIDSPBRIDGE_CACHE_LINE_CHECK:

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When the DSP processes data, the DSP cache controller loads 128-Byte chunks (lines) from SDRAM and writes the data back in 128-Byte chunks. If a DMM buffer does not start and end on a 128-Byte boundary, the data preceding the start address (SA) from the 128-Byte boundary to the SA and the data at addresses trailing the end address (EA) from the EA to the next 128-Byte boundary will be loaded and written back as well. This can lead to heap corruption. Say Y, to enforce the check for 128 byte alignment, buffers failing this check will be rejected.



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