CONFIG_BT1_L2_CTL: Baikal-T1 CM2 L2-RAM Cache Control Block

General informations

The Linux kernel configuration item CONFIG_BT1_L2_CTL:

• prompt: Baikal-T1 CM2 L2-RAM Cache Control Block
• type: bool
• depends on: CONFIG_MIPS_BAIKAL_T1 || CONFIG_COMPILE_TEST
• defined in drivers/memory/Kconfig
• found in Linux kernels: 5.8–5.19, 6.0–6.8, 6.9-rc+HEAD

Help text

Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU resides Coherency Manager v2 with embedded 1MB L2-cache. It's possible to tune the L2 cache performance up by setting the data, tags and way-select latencies of RAM access. This driver provides a dt properties-based and sysfs interface for it.

Hardware

LKDDb

Raw data from LKDDb:

• lkddb of "" "" "baikal,bt1-l2-ctl" : CONFIG_BT1_L2_CTL CONFIG_MEMORY : drivers/memory/bt1-l2-ctl.c # in 5.8–5.19, 6.0–6.8, 6.9-rc+HEAD
• lkddb platform "bt1-l2-ctl" : CONFIG_BT1_L2_CTL CONFIG_MEMORY : drivers/memory/bt1-l2-ctl.c # in 5.8–5.19, 6.0–6.8, 6.9-rc+HEAD

Sources

This page is automaticly generated with free (libre, open) software lkddb(see lkddb-sources).

The data is retrived from:

• Linux kernel
• Linux Kernel Driver DataBase (LKDDb)

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